1. Field of the Invention
The present invention relates to a highly integrated semiconductor connecting device and more particularly to improvements in the degree of integration of a semiconductor device along with a semiconductor connecting device.
2. Description of the Prior Art
For convenience's sake, the description of a conventional connecting device and method is confined to a connecting device comprising a bit line connected with a drain region in the structure of a dynamic random access memory (DRAM) cell, in which a bit line connected with the drain region is formed in advance of a capacitor connected with a source region.
Generally, for the sake of forming a gate region and source/drain electrodes in one active region and connecting a bit line with the drain region in advance of forming a charge storage electrode contact in the source region, the bit line is positioned above a device separation insulating film which is between source regions in such a way as not to be placed above a source region or to minimally overlap with the source electrode. However, in case a bit line contact and a charge storage electrode contact, when forming a bit line connected with the drain region, are linearly positioned on the same line with the bit line, since the bit line is sufficiently connected with the bit line contact formed in the drain region and the neighboring bit lines are spaced apart, the bit line neighboring the bit line connected with the drain region is positioned above the neighboring source region.
Next, a conventional DRAM cell is described with reference to the figures.
Referring initially to FIG. 1, there is a schematic plan view showing only important mask layers for fabricating a DRAM cell, in which a bit line connected with a drain region is formed in advance of a capacitor connected with a source region. While reference numeral 1 designates an active region mask in the figure, reference numerals 2, 3 and 4 designate a bit line contact mask, a bit line mask and a charge storage electrode contact mask, respectively. As illustrated in this figure, the drain region which is formed at a lower part than the source region in an active region la is connected with the bit line 3, so that the bit line 3 is scarcely positioned above the source region in which the charge storage electrode contact 4 is located. However, as the drain region is extended below the source region in which the charge storage electrode 4 is formed, two active regions 1b and 1c positioned below the drain region have to be located at some distance from each other in order that the drain region is kept apart from the active regions positioned below it. This causes the area of the cell to increase.
For a more detailed description, reference is made to FIGS. 2A to 2C, which are schematic cross-sectional views illustrating the steps for forming the bit line in a DRAM cell, taken generally through section line A--A' of FIG. 1.
First, as shown in FIG. 2A, over a predetermined portion of a semiconductor substrate 5, an active region and a device separation insulating film 6 are formed. Thereafter, over the active region there is the formation of a gate region (not shown), a source region (not shown) and a drain region 7. An interlayer insulating film 8 is formed on the resulting structure. At this time, the active region where the drain region is formed is formed in such a way as to extend below another active region where the source region is formed (refer to FIG. 1).
Subsequently, a bit line contact hole is formed on a predetermined portion of the drain region 7 and then, a conductive material for bit line 14 is deposited over the resulting structure, as shown in FIG. 2B. As a result of later process steps, the bit line contact will be positioned below the charge storage electrode contact formed in the source region, as shown in FIG. 1.
Finally, using the bit line mask 3, the conductive material for bit line 14 is etched so as to form a bit line 16, as shown in FIG. 2C. The bit line is connected with the drain region 7 which is formed above the active region where the source region is formed, so that the bit line 16 is scarcely positioned above the source where the charge storage electrode is formed.
However, by the above conventional method, the drain region is formed in such a way as to keep apart the two neighboring active regions linearly positioned below the drain region which are forced to be at some distance from each other, causing the area of cell to increase.